wafer.space Community - Not bad for starters

09:45

PDN is not yet connected between the pad ring and the core. Routing is also currently erroring out.

09:45

This includes several hacks on top of the PDK that need to be upstreamed, as well as changes to the LibreLane padring generation script, which needs to be made more generic to support gf180mcu by default.

09:46

Other than that you can simply set the die size and the I/O cells on each side.

What is exactly it that I’m looking at here?

09:46

I mean (edited)

09:46

I see TT pin names

Yes, the padring uses the same pinout as a tiny tapeout project. You could basically just drop it in there and produce a very expensive TT project/chip. I ported the padring from my IHP LibreLane workshop, see the bonus exercise: https://github.com/FPGA-Research/heichips25-workshop/tree/main

Oh, that’s an interesting repo in general!

10:44

You say this requires changes to both the PDK and the padring script. Are you working on getting those upstreamed right now?

Fyi, I have a preliminary padframe setup for the Synopsys shuttle in this repo: https://github.com/htfab/ttgf0p1-poc

Oh

10:53

Very good

10:53

Is the total die size of that compatible with wafer.space, though? Or do we not know that yet?

I tried going through the IHP LibreLane workshop repo, but using the gf180 PDK. Only a few slight tweaks to the configs were required. Can follow the instructions fine otherwise. Good stuff.

The Synopsys shuttle die size is not compatible with wafer.space, it's smaller

Eventually, this all needs to be upstreamed.

16:26

@htamas How did you deal with Yosys not reading in the I/O cell Verilog? As a workaround I created a separate blackbox library. Or did you just read the liberty?

16:26

For wafer.space, we will probably keep the same die size as Caravel, since we have all the dimensions for the reticle. (And you could still tapeout Caravel if you want.)

16:27

@Tholin Glad to hear you like it! You can even have separate sections for each PDK in the config.

Leo Moser (mole99)

@htamas How did you deal with Yosys not reading in the I/O cell Verilog? As a workaround I created a separate blackbox library. Or did you just read the liberty?

Yes, I just added "EXTRA_LIBS": ["pdk_dir::libs.ref/gf180mcu_fd_io/lib/gf180mcu_fd_io__tt_025C_5v00.lib"] to the config (as well as similar EXTRA_LEFS and EXTRA_GDS_FILES entries for later steps in the flow)

htamas

Fyi, I have a preliminary padframe setup for the Synopsys shuttle in this repo: https://github.com/htfab/ttgf0p1-poc

Trying to make something based off of this. Struggling my way through, one flow error at a time! Currently making it to Generate PDN before error.

htamas

Yes, I just added "EXTRA_LIBS": ["pdk_dir::libs.ref/gf180mcu_fd_io/lib/gf180mcu_fd_io__tt_025C_5v00.lib"] to the config (as well as similar EXTRA_LEFS and EXTRA_GDS_FILES entries for later steps in the flow)

I see, thanks! In the padring branch the I/O cell views are set up directly in the PDK config similar to the standard cells.

1

htamas

Fyi, I have a preliminary padframe setup for the Synopsys shuttle in this repo: https://github.com/htfab/ttgf0p1-poc

Quick question. How did you derive these values? I get flow errors if I try to mess with the die size or any of these, but I kinda need to.

Tholin

Quick question. How did you derive these values? I get flow errors if I try to mess with the die size or any of these, but I kinda need to.

IO_LENGTH & IO_WIDTH come from the io cells in the gf180mcu_fd_io library IO_OFFSET, MAX_NUM_PADS_HORIZONTAL and MAX_NUM_PADS_VERTICAL are to reproduce the exact pad locations of Mehdi's padframe as they are constraints of the Synopsys shuttle

17:10

(there is also DIE_AREA from build.py that factors into the calculations)

17:11

Do you only get flow errors if you change the values?

htamas

Do you only get flow errors if you change the values?

Yep. It goes "Unable to fill gap completely in row IO_NORTH".

Tholin

Yep. It goes "Unable to fill gap completely in row IO_NORTH".

The space between two pads has to be completely filled with filler cells. In my case it was 25 microns so it was enough to use "fill10" and "fill5". If the free space between your pins is not divisible by 5 microns you might have to add "fill1" as well (1 micron wide) and possibly "fillnc" (0.1 micron wide).